`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/05/13 17:40:37
// Design Name: 
// Module Name: decoder
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module decoder(
input logic [31:0] HADDR,
input logic HREADY0,
input logic HREADY1,
input logic HREADY2,
input logic HREADY3,
input logic [1:0] HRESP0,
input logic [1:0] HRESP1,
input logic [1:0] HRESP2,
input logic [1:0] HRESP3,
output logic HSEL0,
output logic HSEL1,
output logic HSEL2,
output logic HSEL3,
output logic HREADY,
output logic [1:0] HRESP
    );
//master-->slave
always_comb
case(HADDR[31:30])
    2'd0:{HSEL3,HSEL2,HSEL1,HSEL0}=4'b0001;
	2'd1:{HSEL3,HSEL2,HSEL1,HSEL0}=4'b0010;
	2'd2:{HSEL3,HSEL2,HSEL1,HSEL0}=4'b0100;
	2'd3:{HSEL3,HSEL2,HSEL1,HSEL0}=4'b1000;
endcase
//slave-->master
always_comb
case(HADDR[31:30])
    2'd0:begin
	        HRESP=HRESP0;
			HREADY=HREADY0;
		 end
	2'd1:begin
	        HRESP=HRESP1;
			HREADY=HREADY1;
		 end
	2'd2:begin
	        HRESP=HRESP2;
			HREADY=HREADY2;
		 end
	2'd3:begin
	        HRESP=HRESP3;
			HREADY=HREADY3;
		 end
endcase

endmodule
